1. Field of the Invention
The invention relates generally to data processing systems and methods and more particularly to systems and methods for controlling the manner in which multiple agents such as computer processors access a resource such as a communication bus in order to improve the distribution of accesses by the various agents and to thereby reduce congestion and delays related to accessing the resource.
2. Related Art
Computer systems are becoming increasingly powerful, and are used not only for scientific and business purposes, but also for entertainment purposes. For instance, some computer systems are used with multimedia applications to present information to a user in the form of sounds, music, still images, video images, and the like. Some computer systems are optimized for these multimedia applications and, in fact, some computer systems are designed exclusively for multimedia applications such as games.
Computer systems that are designed to execute multimedia game applications and other multimedia applications often make use of more than a single processor. These systems may have multiple processors, where one or more of the processors can be dedicated to performing different types of functions. For example, one processor may handle mathematical computations or control functions, while another processor handles video generation and yet another processor handles sound generation. The separation of the responsibilities assigned to each of the processors (or groups of processors) allows the processors to be optimized for that particular types of the functions for which they are responsible. The different processors are typically interconnected and operate interactively to coordinate the different functions of the system.
Typically, the different processors that are operable in a multimedia game system are each connected to a common bus. This bus enables the common control on the processors to coordinate their activities and also enables the exchange of data between them. Additionally, the bus provides a means for communication of the outputs of the different processors to the appropriate output devices. Because of the many functions that must be performed by the multiple processors, there is a great deal of information that is communicated by this bus. Because there may be periods during which many of the processors may be attempting to access the bus to communicate commands or other data to various other parts of the system, there is potential for congestion on the bus. In other words, the processors may attempt to communicate an amount of information on the bus that exceeds the capacity of the bus.
There is therefore a need to implement a mechanism to prevent congestion on the bus. Conventionally, access to the bus by the various processors has been controlled by putting a hard limit on accesses to the bus by each of the processors. For example, there might be four processors coupled to the bus. Each of the processors would be allowed a predetermined number of accesses to the bus (e.g., commands issued to the bus) in a given period. For each processor, once at the number of accesses reached the predetermined number, that processor with no longer be allowed to access the bus.
This mechanism for controlling access to the bus, however, is not ideal for a number of reasons. One of these reasons is that the pattern of accesses by the different processors may be irregular. This may be problematic because, in multimedia systems, it may be necessary to provide access and a more regular fashion in order to enable the processors to meet the real-time demands of the multimedia application that is being executed. This problem may be illustrated by an example.
Referring to FIG. 1, a graph illustrating the bandwidth utilized by a particular processor is shown. It is assumed for the purposes of this figure that there are four processors, each of which is allowed to access the bus in a round robin fashion until it reaches its allocated number of accesses. It is further assumed that the processor for which the bandwidth usage is graphed in FIG. 1 (processor A) needs 50 percent of the bus's bandwidth.
As indicated above, the bus accesses for processor A are shown in the figure (as curve 110). Initially (between time t0 and t1), none of the processors has reached its predetermined allocation and therefore all four processors take turns accessing the bus. Processor A therefore gets 25 percent of the bandwidth. At time t1, three of the processors reached their allocations and are therefore prohibited from accessing the bus for the remainder of the period (i.e., until time t2). Thus, only processor A is allowed to access the bus during the period from time t1 to t2. As noted above, this may cause problems, in that processor A may need more than 25% of the bus bandwidth during the period from t0 to t1, and the other processors may need more than 0% of the bandwidth during the period from t1 to t2, in order to meet the real-time requirements for each of the processors.